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    Please use this identifier to cite or link to this item: http://ir.nknu.edu.tw/ir/handle/987654321/22005


    題名: A 0.5 V Phase-Locked Loop in 90nm CMOS Process
    Authors: Kuo-Hsing Cheng;Jing-Shiuan Huang;Yu-Chang Tsai;Chao-Chang Chiu;Yu-Lung Lo
    羅有龍
    Date: 2009-08
    Issue Date: 2014-11-12 16:25:06 (UTC+8)
    關聯: Proc. of the 20th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2009
    Appears in Collections:[電子系] 羅有龍
    [電子工程學系] 會議論文

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