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    Items for Author "Yu-Lung Lo" 

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    Showing 47 items.

    Collection Date 題名 Authors Bitstream
    [特殊教育系] 研究計畫 2015-08 台灣地區成人其標準及多頻率鼓室圖常模之建立 羅意琪; Yu-Lung Lo
    [電子工程學系] 會議論文 2013-08 A High-Linearity All-Digital Temperature Sensor With Ring Oscillator Yu-Lung Lo; Yu-Ting Chiu; Wei-Bin Yang; Chao-Chang Chiu; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2013-04 A GHz Full-Division-Range Programmable Divider with Output Duty-Cycle Improved Yu-Lung Lo; Jhih-WeiTsai; Han-Ying Liu; Wei-Bin Yang; 羅有龍
    [電子工程學系] 會議論文 2012-06 A Fast-Lock Analog Multiphase Delay-Locked Loop Using a Dual-Slope Technique Pin-Tseng Chen; Chia-Chen Chang; Han-Ying Liu; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2011-12 An All-Digital DLL with Dual-Loop Control for Multiphase Clock Generator Yu-Lung Lo; Pei-Yuan Chou; Hsiang-Hui Cheng; Shu-Fen Tsai; Wei-Bin Yang; 羅有龍
    [電子工程學系] 會議論文 2011-12 Supply Voltage and Temperature Insensitive Current Reference for the 4 MHz Oscillator Chi-Hsiung Wang; Cheng-Feng Lin; Wei-Bin Yang; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2011-12 Temperature Insensitive Current Reference for the 6.27 MHz Oscillator Ching-Tsan Cheng; Zheng-Yi Huang; Wei-Bin Yang; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2010-11 A New Dynamic Fast-Settling Low Dropout Regulator with Programmable Output Voltage Hsiang-Hsiung Chang; Jsung-Mo Shen; Wei-Bin Yang; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2009-12 A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller Wan-Lun Gao; Yang Wei-Bin; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2009-12 A Low Power Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator Jsung-Mo Shen; Wei-Bin Yang; Chang-Yu Hsieh; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2009-09 Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique Ting-Sheng Chao; Yu-Lung Lo; Wei-Bin Yang; Kuo-Hsing Cheng; 羅有龍
    [電子工程學系] 會議論文 2009-08 A 0.5 V Phase-Locked Loop in 90nm CMOS Process Kuo-Hsing Cheng; Jing-Shiuan Huang; Yu-Chang Tsai; Chao-Chang Chiu; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2009-08 A Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator Jsung-Mo Shen; Wei-Bin Yang; Chang-Yu Hsieh; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2008-08 Ultra-Low-Voltage Phase-Locked Loop with Bulk-Input VCO Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Jiunn-Way Miaw; Jing-Shiuan Huang; Kuo-Hsing Cheng; 羅有龍
    [電子工程學系] 會議論文 2008-04 Spread-Spectrum Clock Generator Using Fractional–N PLL Controlled Delta-Sigma Modulator for Serial-ATA III Kuo-Hsing Cheng; Cheng-Laing Hung; Chih-Hsien Chang; Yu-Lung Lo; Wei-Bin Yang; Jiunn-Way Miaw; 羅有龍
    [電子工程學系] 會議論文 2007-12 A Phase Interpolator for Sub-1V and High Frequency for Clock and Data Recovery Kuo-Hsing Cheng; Pei-Kai Tseng; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2006-12 A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler Ting-Sheng Jau; Wei-Bin Yang; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2006-05 A 100MHz-1GHz Adaptive Bandwidth Phase-Locked Loop in 90nm Process Kuo-Hsing Cheng; Kai-Fei Chang; Yu-Lung Lo; Ching-Wen Lai; Yuh-Kuang Tseng; 羅有龍
    [電子工程學系] 會議論文 2005-09 A Fast-Lock Mixed-Mode DLL with Wide-Range Operation and Multiphase Outputs Kuo-Hsing Cheng; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2005-05 A Phase-detect Synchronous Mirror Delay for Fast Clock Skew-compensation Circuits Kuo-Hsing Cheng; Chen-Lung Wu; Yu-Lung Lo; Chia-Wei Su; 羅有龍
    [電子工程學系] 會議論文 2004-08 A CMOS VCO for 1V, 1GHz PLL Applications Kuo-Hsing Cheng; Ching-Wen Lai; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2004-08 A Phase-Locked Pulse Width Control Loop with Programmable Duty Cycle Kuo-Hsing Cheng; Chia-Wei Su; Cheng-Lung Wu; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2004-08 A 2.2 GHz Programmable DLL-Based Frequency Multiplier for SOC Applications Kuo-Hsing Cheng; Shu-Ming Chang; Yu-Lung Lo; Shu-Yu Jiang; 羅有龍
    [電子工程學系] 會議論文 2004-08 A Fast-Lock Mixed-Mode Delay-Locked Loop with Wide-Range Operation and Multiphase Outputs Kuo-Hsing Cheng; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2004-05 A Fast-lock DLL with Power-on Reset Circuit Kuo-Hsing Cheng; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2003-06 A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation Kuo-Hsing Cheng; Yu-Lung Lo; Wen-Fang Yu; Shu-Yin Hung; 羅有龍
    [電子工程學系] 會議論文 2002-07 A Novel Power-On Reset Circuit Without Capacitor Kuo-Hsing Cheng; Yu-Lung Lo; Wei-Bin Yang; 羅有龍
    [電子工程學系] 期刊論文 2013-02 A Low-Area Full-Division-Range Programmable Frequency Divider with a 50% Duty-Cycle Output Yu-Lung Lo; Jhih-Wei Tsai; 羅有龍
    [電子工程學系] 期刊論文 2012-12 A 0.7-V Input Output-capacitor-free Digitally Controlled Low-dropout Regulator with High Current Efficiency in 0.35-?m CMOS Technology Yu-Lung Lo; Wei-Jen Chen; 羅有龍
    [電子工程學系] 期刊論文 2012-10 A Low-Area Fast-Lock Analog Delay-Locked Loop Using a Dual-Slope Technique for Multiphase Clock Generator Yu-Lung Lo; Pin-Tseng Chen; Chia-Chen Chan; Han-Ying Liu; 羅有龍
    [電子工程學系] 期刊論文 2012-06-01 A 50ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit Yu-Lung Lo; Pin-Tseng Chen; Chia-Chen Chan; Han-Ying Liu; 羅有龍
    [電子工程學系] 期刊論文 2011-06 The High-Performance and Low-Power CMOS Output Driver Design Ching-Tsan Chen; Chi-Hsiung Wang; Pei-Hsuan Liao; Wei-Bin Yang; Yu-Lung Lo; 羅有龍
    [電子工程學系] 期刊論文 2011-03 A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip Kuo-Hsing Chen; Yu-Chang Tsai; Yu-Lung Lo; Jing-Shiuan Huang; 羅有龍
    [電子工程學系] 期刊論文 2010-12 Dynamic Frequency Tracking and Phase Error Compensation Clock De-skew Buffer Kuo-Hsing Cheng; Kai-Wei Hong; Yu-Lung Lo; Chen-Lung Wu; Chien-Hsien Lee; 羅有龍
    [電子工程學系] 期刊論文 2010-03 A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output Wei-Bin Yang; Yu-Lung Lo; Ting-Sheng Chao; 羅有龍
    [電子工程學系] 期刊論文 2009-06 High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng; 羅有龍
    [電子工程學系] 期刊論文 2009-05 Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng; 羅有龍
    [電子工程學系] 期刊論文 2009-02 Vernier Caliper and Equivalent-Signal Sampling for Built-in Jitter Measurement System Shu-Yu Jiang; Chan-Wei Huang; Yu-Lung Lo; Kuo-Hsing Cheng; 羅有龍
    [電子工程學系] 期刊論文 2007-11 Analysis and Design of Ultra Low VDD Circuit Ting-Sheng Chao; Chung-Yu Chang; Yu-Lung Lo; 羅有龍
    [電子工程學系] 期刊論文 2007-07 A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency Range Selector for Multiphase Clock Generator Kuo-Hsing Chen; Yu-Lung Lo; 羅有龍
    [電子工程學系] 期刊論文 2004-09 A Fast-Lock DLL with Power-On Reset Circuit Kuo-Hsing Cheng; Yu-Lung Lo; Shu-Yu Jiang; 羅有龍
    [電子工程學系] 研究計畫 2014-08 具供應電壓抑制與製程補償之高線性度全數位式溫度感測器 羅有龍; Yu-Lung Lo
    [電子工程學系] 研究計畫 2013-08 具同步且寬頻之全數位式責任週期校正器研製 羅有龍; Yu-Lung Lo
    [電子工程學系] 研究計畫 2012-12-16 智慧型電熱水器電路設計 羅有龍; Yu-Lung Lo
    [電子工程學系] 研究計畫 2012-08 超低電壓操作且高電流效率之全數位控制低壓降線性穩壓器研製 羅有龍; Yu-Lung Lo
    [電子工程學系] 研究計畫 2011-08 以延遲鎖定迴路為基礎之低功率小面積全數位可程式化時脈產生器研製 羅有龍; Yu-Lung Lo
    [電子工程學系] 研究計畫 2010-10 具多重相位輸出之寬頻全數位延遲鎖定迴路研製 羅有龍; Yu-Lung Lo

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