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    Items for Author "Kuo-Hsing Cheng" 

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    Showing 20 items.

    Collection Date 題名 Authors Bitstream
    [電子工程學系] 會議論文 2009-09 Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique Ting-Sheng Chao; Yu-Lung Lo; Wei-Bin Yang; Kuo-Hsing Cheng; 羅有龍
    [電子工程學系] 會議論文 2009-08 A 0.5 V Phase-Locked Loop in 90nm CMOS Process Kuo-Hsing Cheng; Jing-Shiuan Huang; Yu-Chang Tsai; Chao-Chang Chiu; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2008-08 Ultra-Low-Voltage Phase-Locked Loop with Bulk-Input VCO Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Jiunn-Way Miaw; Jing-Shiuan Huang; Kuo-Hsing Cheng; 羅有龍
    [電子工程學系] 會議論文 2008-04 Spread-Spectrum Clock Generator Using Fractional–N PLL Controlled Delta-Sigma Modulator for Serial-ATA III Kuo-Hsing Cheng; Cheng-Laing Hung; Chih-Hsien Chang; Yu-Lung Lo; Wei-Bin Yang; Jiunn-Way Miaw; 羅有龍
    [電子工程學系] 會議論文 2007-12 A Phase Interpolator for Sub-1V and High Frequency for Clock and Data Recovery Kuo-Hsing Cheng; Pei-Kai Tseng; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2006-05 A 100MHz-1GHz Adaptive Bandwidth Phase-Locked Loop in 90nm Process Kuo-Hsing Cheng; Kai-Fei Chang; Yu-Lung Lo; Ching-Wen Lai; Yuh-Kuang Tseng; 羅有龍
    [電子工程學系] 會議論文 2005-09 A Fast-Lock Mixed-Mode DLL with Wide-Range Operation and Multiphase Outputs Kuo-Hsing Cheng; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2005-05 A Phase-detect Synchronous Mirror Delay for Fast Clock Skew-compensation Circuits Kuo-Hsing Cheng; Chen-Lung Wu; Yu-Lung Lo; Chia-Wei Su; 羅有龍
    [電子工程學系] 會議論文 2004-08 A CMOS VCO for 1V, 1GHz PLL Applications Kuo-Hsing Cheng; Ching-Wen Lai; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2004-08 A Phase-Locked Pulse Width Control Loop with Programmable Duty Cycle Kuo-Hsing Cheng; Chia-Wei Su; Cheng-Lung Wu; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2004-08 A 2.2 GHz Programmable DLL-Based Frequency Multiplier for SOC Applications Kuo-Hsing Cheng; Shu-Ming Chang; Yu-Lung Lo; Shu-Yu Jiang; 羅有龍
    [電子工程學系] 會議論文 2004-08 A Fast-Lock Mixed-Mode Delay-Locked Loop with Wide-Range Operation and Multiphase Outputs Kuo-Hsing Cheng; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2004-05 A Fast-lock DLL with Power-on Reset Circuit Kuo-Hsing Cheng; Yu-Lung Lo; 羅有龍
    [電子工程學系] 會議論文 2003-06 A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation Kuo-Hsing Cheng; Yu-Lung Lo; Wen-Fang Yu; Shu-Yin Hung; 羅有龍
    [電子工程學系] 會議論文 2002-07 A Novel Power-On Reset Circuit Without Capacitor Kuo-Hsing Cheng; Yu-Lung Lo; Wei-Bin Yang; 羅有龍
    [電子工程學系] 期刊論文 2010-12 Dynamic Frequency Tracking and Phase Error Compensation Clock De-skew Buffer Kuo-Hsing Cheng; Kai-Wei Hong; Yu-Lung Lo; Chen-Lung Wu; Chien-Hsien Lee; 羅有龍
    [電子工程學系] 期刊論文 2009-06 High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng; 羅有龍
    [電子工程學系] 期刊論文 2009-05 Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng; 羅有龍
    [電子工程學系] 期刊論文 2009-02 Vernier Caliper and Equivalent-Signal Sampling for Built-in Jitter Measurement System Shu-Yu Jiang; Chan-Wei Huang; Yu-Lung Lo; Kuo-Hsing Cheng; 羅有龍
    [電子工程學系] 期刊論文 2004-09 A Fast-Lock DLL with Power-On Reset Circuit Kuo-Hsing Cheng; Yu-Lung Lo; Shu-Yu Jiang; 羅有龍

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