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    Please use this identifier to cite or link to this item: http://ir.nknu.edu.tw/ir/handle/987654321/21999

    題名: A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller
    Authors: Wan-Lun Gao;Yang Wei-Bin;Yu-Lung Lo
    Date: 2009-12
    Issue Date: 2014-11-12 16:25:01 (UTC+8)
    關聯: IEEE International Symposium on Integrated Circuits (ISIC), pp. 562-565, Dec. 2009. (EI)
    Appears in Collections:[電子工程學系] 會議論文
    [電子系] 羅有龍

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