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    Please use this identifier to cite or link to this item: http://ir.nknu.edu.tw/ir/handle/987654321/2118

    題名: 磷化銦鎵/砷化銦鎵摻雜通道高電子遷移率場效電晶體之研究及邏輯應用
    Investigation and Logic Application of InGaP/InGaAsDoped-Channel High Electron MobilityField-Effect Transistors
    Authors: 翁子晏
    Tzu-Yen Weng
    貢獻者: 蔡榮輝
    Jung-Hui Tsai
    Keywords: 摻雜通道;直接耦合電晶體邏輯
    Date: 2007-07-04
    Issue Date: 2010-05-14
    Abstract: 本論文將以摻雜通道擬晶性異質結構場效電晶體為基礎,提出新型的增強/空乏式共積體化元件,使其具有高閘極能障高度、高導通壓、高線性轉導值、低飽和電壓、寬廣閘極電壓操作範圍及優異的高頻特性,而且於反向器邏輯電路應用時,同時具有極大的雜訊邊界。
    In this thesis, based on InGaP/InGaAs doped-channel pseudomorphic heterostructure field-effect transistors (HFETs), novel integrated enhancement/depletion-mode devices are addressed. The devices could exhibit high gate barrier, high turn-on voltage, high linearly transconductance, lower saturation voltage, broad gate voltage swing, and excellent high frequency performance. Furthermore the relatively large noise margins are achieved in direct-coupled field-effect transistor logic (DCFL) application. The simulation tool silvaco is used to simulate the performances of the InGaP/InGaAs doped-channel high electron mobility field-effect transistors (DC-HEMTs).

    First, the InGaP/InGaAs integrated enhancement/depletion DC-HEMTs on the identical chip are first demonstrated. Due to the higher electron mobility, higher peak electron velocity and lower effective mass of InGaAs material, it is favorable to use an InGaAs to replace the GaAs as a channel layer to improve the device performances. As to the depletion-mode device, the upper doped-channel layer is entirely depleted and the depletion region is justly immersed into the lower doped-channel layer at equilibrium .It forms subband and two-dimensional electron gas (2DEG) in the low InGaAs strain channel, which increase the channel concentration. On the other hand, for the enhancement-mode device the doped-channel layer is completely depleted at equilibrium and the active channel appear under sufficient large gate forward bias.
    Second, the monolithic integration of enhancement and depletion-mode FETs in the same chip provides the reduction of fabrication complexity by the implement of inverters. The power supply voltage can be effectively reduced resulting from the low drain-to-source (D-S) saturation voltage. The integrated DC-HEMTs exhibit the larger noise margins than the HEMTs for DCFL application because the saturation voltages of the integrated device are relatively small.
    Appears in Collections:[物理學系] 博碩士論文
    [電子系] 蔡榮輝

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