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    Please use this identifier to cite or link to this item: http://ir.nknu.edu.tw/ir/handle/987654321/2118


    題名: 磷化銦鎵/砷化銦鎵摻雜通道高電子遷移率場效電晶體之研究及邏輯應用
    Investigation and Logic Application of InGaP/InGaAsDoped-Channel High Electron MobilityField-Effect Transistors
    Authors: 翁子晏
    Tzu-Yen Weng
    貢獻者: 蔡榮輝
    Jung-Hui Tsai
    Keywords: 摻雜通道;直接耦合電晶體邏輯
    doped-channel;DCFL
    Date: 2007-07-04
    Issue Date: 2010-05-14
    Abstract: 本論文將以摻雜通道擬晶性異質結構場效電晶體為基礎,提出新型的增強/空乏式共積體化元件,使其具有高閘極能障高度、高導通壓、高線性轉導值、低飽和電壓、寬廣閘極電壓操作範圍及優異的高頻特性,而且於反向器邏輯電路應用時,同時具有極大的雜訊邊界。
    我們利用Silvaco軟體來模擬磷化銦鎵/砷化銦鎵摻雜通道高電子遷移率場效電晶體,分別討論空乏式與增強式這兩種元件與其反向器邏輯電路。以空乏式磷化銦鎵/砷化銦鎵摻雜通道高電子遷移率場效電晶體而言,其具有傳統摻雜通道場效電晶體佳的線性度且具有高電子遷移率電晶體(HEMT)載子調變的優點,因為通道中二維電子雲氣之載子可隨閘極正偏壓而調變增加,使其摻雜通道內的有效濃度增加,線性區的電流將快速上升,且汲極和源極至閘極間的間隔僅有1μm,故寄生電阻極低,汲極與源極之間(D-S)飽和電壓有效降低,由於低飽和電壓的特性,使得直接耦合式電晶體邏輯(DCFL)的供應電壓可降低,而增強式元件亦有如此特性,所以磷化銦鎵/砷化銦鎵高電子遷率場效電晶體用來做反向器邏輯電路有極高的雜訊邊界,另外增強式元件由於砷化銦鎵上層摻雜通道已完全去除,故此元件僅具有單一層通道。因金-半蕭基接面使摻雜通道完全空乏,其主動通道須於正的閘極電壓時方能出現,此增強式元件因通道較接近閘極,因此轉導值較為提升;然而通道為單一摻雜層,其最大的飽合電流密度較空乏式元件為低。
    In this thesis, based on InGaP/InGaAs doped-channel pseudomorphic heterostructure field-effect transistors (HFETs), novel integrated enhancement/depletion-mode devices are addressed. The devices could exhibit high gate barrier, high turn-on voltage, high linearly transconductance, lower saturation voltage, broad gate voltage swing, and excellent high frequency performance. Furthermore the relatively large noise margins are achieved in direct-coupled field-effect transistor logic (DCFL) application. The simulation tool silvaco is used to simulate the performances of the InGaP/InGaAs doped-channel high electron mobility field-effect transistors (DC-HEMTs).

    First, the InGaP/InGaAs integrated enhancement/depletion DC-HEMTs on the identical chip are first demonstrated. Due to the higher electron mobility, higher peak electron velocity and lower effective mass of InGaAs material, it is favorable to use an InGaAs to replace the GaAs as a channel layer to improve the device performances. As to the depletion-mode device, the upper doped-channel layer is entirely depleted and the depletion region is justly immersed into the lower doped-channel layer at equilibrium .It forms subband and two-dimensional electron gas (2DEG) in the low InGaAs strain channel, which increase the channel concentration. On the other hand, for the enhancement-mode device the doped-channel layer is completely depleted at equilibrium and the active channel appear under sufficient large gate forward bias.
    Second, the monolithic integration of enhancement and depletion-mode FETs in the same chip provides the reduction of fabrication complexity by the implement of inverters. The power supply voltage can be effectively reduced resulting from the low drain-to-source (D-S) saturation voltage. The integrated DC-HEMTs exhibit the larger noise margins than the HEMTs for DCFL application because the saturation voltages of the integrated device are relatively small.
    Appears in Collections:[物理學系] 博碩士論文
    [電子系] 蔡榮輝

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