English  |  正體中文  |  简体中文  |  Items with full text/Total items : 16335/24215 (67%)
Visitors : 11041073      Online Users : 188
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    蔡榮輝 [151/273]
    黃智裕 [87/175]
    林尚亭 [9/17]
    黃嘉宏 [16/23]
    吳建銘 [24/51]
    王瑞祿 [86/163]
    洪群雄 [20/69]
    楊宜霖 [11/21]

    Collection Statistics

    近3年內發表的文件: 0(0.00%)
    含全文筆數: 41(80.39%)

    文件下載次數統計
    下載大於0次: 41(100.00%)
    下載大於100次: 41(100.00%)
    檔案下載總次數: 19436(8.98%)

    最後更新時間: 2019-10-15 02:44


    Top Upload

    Loading...

    Top Download

    Loading...

    Recent Submissions

    RSS Feed RSS Feed

    Jump to: [Chinese Items]   [0-9]   [ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z ]
    or enter the first few letters:   

    Showing items 1-25 of 51. (3 Page(s) Totally)
    1 2 3 > >>
    View [10|25|50] records per page

    Date題名Authors
    2009-08 A 0.5 V Phase-Locked Loop in 90nm CMOS Process Kuo-Hsing Cheng; Jing-Shiuan Huang; Yu-Chang Tsai; Chao-Chang Chiu; Yu-Lung Lo; 羅有龍
    2011-03 A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip Kuo-Hsing Chen; Yu-Chang Tsai; Yu-Lung Lo; Jing-Shiuan Huang; 羅有龍
    2012-12 A 0.7-V Input Output-capacitor-free Digitally Controlled Low-dropout Regulator with High Current Efficiency in 0.35-?m CMOS Technology Yu-Lung Lo; Wei-Jen Chen; 羅有龍
    2006-05 A 100MHz-1GHz Adaptive Bandwidth Phase-Locked Loop in 90nm Process Kuo-Hsing Cheng; Kai-Fei Chang; Yu-Lung Lo; Ching-Wen Lai; Yuh-Kuang Tseng; 羅有龍
    2004-08 A 2.2 GHz Programmable DLL-Based Frequency Multiplier for SOC Applications Kuo-Hsing Cheng; Shu-Ming Chang; Yu-Lung Lo; Shu-Yu Jiang; 羅有龍
    2012-06-01 A 50ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit Yu-Lung Lo; Pin-Tseng Chen; Chia-Chen Chan; Han-Ying Liu; 羅有龍
    2011-12 An All-Digital DLL with Dual-Loop Control for Multiphase Clock Generator Yu-Lung Lo; Pei-Yuan Chou; Hsiang-Hui Cheng; Shu-Fen Tsai; Wei-Bin Yang; 羅有龍
    2007-11 Analysis and Design of Ultra Low VDD Circuit Ting-Sheng Chao; Chung-Yu Chang; Yu-Lung Lo; 羅有龍
    2004-08 A CMOS VCO for 1V, 1GHz PLL Applications Kuo-Hsing Cheng; Ching-Wen Lai; Yu-Lung Lo; 羅有龍
    2006-12 Design of Self-Sampling Based ASK Demodulator for Implantable Microsystem C.S. Alex Gong; C. L. Wu; S. Y. Ho; T. Y. Chen; J. C. Huang; C. W. Su; C. H. Su; Y. Chang; K. H. Cheng; Y. L. Lo; M. T. Shiue; 羅有龍
    2009-05 Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng; 羅有龍
    2009-09 Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique Ting-Sheng Chao; Yu-Lung Lo; Wei-Bin Yang; Kuo-Hsing Cheng; 羅有龍
    2010-12 Dynamic Frequency Tracking and Phase Error Compensation Clock De-skew Buffer Kuo-Hsing Cheng; Kai-Wei Hong; Yu-Lung Lo; Chen-Lung Wu; Chien-Hsien Lee; 羅有龍
    2012-06 A Fast-Lock Analog Multiphase Delay-Locked Loop Using a Dual-Slope Technique Pin-Tseng Chen; Chia-Chen Chang; Han-Ying Liu; Yu-Lung Lo; 羅有龍
    2004-09 A Fast-Lock DLL with Power-On Reset Circuit Kuo-Hsing Cheng; Yu-Lung Lo; Shu-Yu Jiang; 羅有龍
    2004-05 A Fast-lock DLL with Power-on Reset Circuit Kuo-Hsing Cheng; Yu-Lung Lo; 羅有龍
    2004-08 A Fast-Lock Mixed-Mode Delay-Locked Loop with Wide-Range Operation and Multiphase Outputs Kuo-Hsing Cheng; Yu-Lung Lo; 羅有龍
    2005-09 A Fast-Lock Mixed-Mode DLL with Wide-Range Operation and Multiphase Outputs Kuo-Hsing Cheng; Yu-Lung Lo; 羅有龍
    2007-07 A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency Range Selector for Multiphase Clock Generator Kuo-Hsing Chen; Yu-Lung Lo; 羅有龍
    2013-04 A GHz Full-Division-Range Programmable Divider with Output Duty-Cycle Improved Yu-Lung Lo; Jhih-WeiTsai; Han-Ying Liu; Wei-Bin Yang; 羅有龍
    2013-08 A High-Linearity All-Digital Temperature Sensor With Ring Oscillator Yu-Lung Lo; Yu-Ting Chiu; Wei-Bin Yang; Chao-Chang Chiu; Yu-Lung Lo; 羅有龍
    2011-06 The High-Performance and Low-Power CMOS Output Driver Design Ching-Tsan Chen; Chi-Hsiung Wang; Pei-Hsuan Liao; Wei-Bin Yang; Yu-Lung Lo; 羅有龍
    2009-06 High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng; 羅有龍
    2009-12 A Low Power Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator Jsung-Mo Shen; Wei-Bin Yang; Chang-Yu Hsieh; Yu-Lung Lo; 羅有龍
    2012-10 A Low-Area Fast-Lock Analog Delay-Locked Loop Using a Dual-Slope Technique for Multiphase Clock Generator Yu-Lung Lo; Pin-Tseng Chen; Chia-Chen Chan; Han-Ying Liu; 羅有龍

    Showing items 1-25 of 51. (3 Page(s) Totally)
    1 2 3 > >>
    View [10|25|50] records per page

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback